# Almost identical to Makefile except for the use of makefile variables

# define some variable
CC = gcc
CFLAGS = -g -Wall
RM = rm -f

all: ttest

ttest: ttest.o basestats.o
	$(CC) $(CFLAGS) -lm -o ttest ttest.o basestats.o

ttest.o: ttest.c ttest.h basestats.h
	$(CC) $(CFLAGS) -c ttest.c

basestats.o: basestats.c basestats.h
	$(CC) $(CFLAGS) -c basestats.c

clean:
	$(RM) *.o *~